ABSTRACT
The hardware design of the system mainly consisted of the FPGA development board, PC machine and computer display. PC will download a program to the FPGA development board, and then it sends command to the EP2C35F672C6 by the serial port aide. After FPGA development receives the instruction, it will instruct the computer screen to display pictures, and through the serial port assistant to send information to the PC machine[2] . The design of the system block diagram is shown in Figure 1, the
FPGA development board work mainly includes six modules: the clock multiplier module, serial port receiver module, serial transmission module, image data storage control module, VGA interface, VGA display module timing generator selector. The clock multiplier is the use of PLL IP core inside the ring to implement, through frequency doubling method to get the precise value of the clock frequency of 68.25MHZ. And by using the programming method of state machine to implement the design of an asynchronous FIFO based on serial transmitter, ensure the correct data writing and reading, this avoids the happening of the overflow phenomenon. VGA timing generator display module, data memory and a read and write control uses single ROM core to implement, it solves the problem of display data sources and data storage. The image data stored in the core of the ROM, for there is no color converter in the internal of ADV7123 so when the data displays as an RGB signal in memory, it can be transmitted directly to the ADV7123.
