ABSTRACT
In order to realize these advantages for integrated circuit design, there has been much research work on compact modeling for fully depleted SOI MOSFETs [8-22]. These mainstream models are mainly surface potentialbased [8-13], charge-based [14-20], threshold voltagebased [21] or others [22]. The traditional threshold voltage based models have limitations in rising RF circuit design applications because of its discontinuity in derivative and asymmetry, etc [12, 22]. The potentialbased models which express the charge and current in terms of the surface potential and the charge-based models that formulate the terminal charges and drain current with the inversion charge density, have potentials in analog and RF CMOS simulation application [8, 9, 14-17]. This model deal with highly doped and undoped devices with different expressions and the variation of the buried oxide thickness is also neglected by assuming it equal to the front-gate oxide thickness [18, 19]. However, since the thin buried oxide may complicate the technology with loss of speed, the thick-buried-oxide device may be a better design. Thus a unified model considering various structure parameter variations is still lacking for the circuit design applications with fully depleted devices.
