ABSTRACT
This chapter illustrates that a traditional von Neumann computer system is the heterogeneous integration of logic cells, memory chips, and the interconnections. It shows that the equivalent data-transmission route for one merge stage of a bitonic sort. Computing performance can be substantially improved by monolithically integrating several new heterogeneous memory layers on top of logic layers powered by a combination of CMOS and “new switch” transistors. Three-dimensional (3D) packaging has been available for decades in large scale, with interconnections, performance, and energy efficiency. In the 1970s, two fundamental laws became the footstones for the whole industry: Moore’s and Dennard’s scaling laws. 3D integration and packaging has been successful in mainstream devices to increase logic density and to reduce data-movement distances. 3D sequential integration is the next generation of 3D integration technologies; it is also named monolithic 3D (M3D). There are three categories of M3D integration depending on the pitch of tier partitioning: transistor-level, gate-level, and block-level M3D integration.
