ABSTRACT
In this chapter, an overview of the major challenges of the fin field-effect transistor (FinFET) process, device, and circuit design are presented. First of all, the lithography challenges for fin patterning using 193-nm ArF immersion lithography with self-aligned double patterning and self-aligned quadruple patterning are discussed. Then the FinFET process integration challenges related to the gate and spacer patterning, patterning of uniform fins, and the epitaxial SiGe stressor material for raised source-drain formation are overviewed. The major issues for conformal doping in fins, controlling fin dimensions, and wet and dry etch processes for STI formation are discussed. Then the challenges in the high-k and replacement metal-gate processing, and thermal instability of HfO2/silicon interface for the integration of HfO2 as the gate dielectric are discussed. The device technology challenges including width quantization, multiple-V th transistors at a technology node, and optimal crystal orientation in FinFET layout design to achieve high mobility for both nFinFETs and pFinFETs are overviewed. The process and device challenges impose circuit design challenges to control critical dimensions approaching the 3-nm regime.
