ABSTRACT
The simplest MOS gate circuit is an inverter made using a single n-channel MOSFET switch with a pull-up device. Two factors place a practical limit on the fan-in for an MOS NAND circuit. First, scaling the switch transistors by the factor M results in a circuit with a large layout area on the chip if M is large Second, both the static and dynamic performance will be degraded even if the widths of the pull-down transistors are scaled by a factor of M. This is because, under output low conditions, the drain-to-source voltage drops of the lower transistors decrease the gate-to-source biasing for the upper transistors in the M-high stack of switches. General AND-OR-INVERT functions may be implemented by combining parallel and series connected pull-down transistors. An extension of the pass transistor is the CMOS transmission gate.
