ABSTRACT
Dynamic, or clocked, CMOS gates achieve greater speed and allow higher packing densities than the static CMOS circuits discussed so far. Reduced dissipation is associated with lower input capacitances, because each input is connected to a single n-MOS transistor. The basic operation of the dynamic CMOS inverter is illustrated in this chapter. The chapter examines some of the key considerations for dynamic CMOS circuits in detail. Although one approach to sizing transistors in CMOS transistors has been described here, other schemes exist as well. In the dynamic CMOS inverter, the output node is referred to as a soft node. This is because a high output voltage exists only by virtue of the charge stored and is not accompanied by the active drive of a p-MOS pull-up network. The total switched capacitance may be reduced because of the lower input capacitance.
