ABSTRACT
Low-power CMOS has become increasingly important because of the proliferation of portable and hand-held electronic products. The most effective way to reduce the power in CMOS circuitry is to scale down the supply voltage, but this involves a tradeoff with speed. Sometimes multiple supply voltages are used so that critical path circuitry can use higher supply voltages to optimize speed. In low-voltage circuits, it is necessary to scale down the threshold voltages to maintain reasonable dynamic performance. In this chapter, circuit approaches to low-power CMOS design is described, with an emphasis on the principles involved. Other approaches to power reduction in CMOS involve reduction of the switching activity or the load capacitances, or charge recycling. The switching activity can be reduced by clock gating or sleep control techniques. Reduction of the load capacitances can be achieved by scaling of the devices.
