Sequential Logic Design Using Verilog HDL

This chapter provides techniques for designing sequential logic using Verilog hardware description language. Sequential logic circuits consist of combinational logic and storage elements. A synchronous sequential machine requires a state diagram or state table for its precise description. The state diagram depicts the sequence of events that must occur in order for the machine to perform the functions which are defined in the machine specifications. Synchronous registers are designed using storage elements. Each cell of a register stores one bit of binary information. Counters are fundamental hardware devices used in the design of digital systems and have a finite number of states. The state of the counter is interpreted as an integer with respect to a modulus. In pulse-mode asynchronous sequential machines, state changes occur on the application of input pulses which trigger the storage elements. The duration of the pulse is less than the propagation delay of the storage elements and associated logic gates.