Architecture of the on-chip debug module for a multiprocessor system

ABSTRACT:   This paper proposes an architecture description of the on-chip debug module aiming at a multiprocessor system. Some special function registers were used for setting the debugging mode and debugging flow control. Through the internal priority register setting, different processors can be set with or without different priory level, by which the different debugging structure can be realized. Internal arbitration mechanism handles the competition between different processors and decides the access order for different processors. Finally, all these techniques are integrated to make the on-chip debugging operation more efficient and flexible.