Off-Chip and In-Chip Communications for FPGA Systems

This chapter describes the connectivity of embedded microprocessor cores. It deals with structured ways of communicating internal modules within a field-programmable gate arrays (FPGAs). Three types of connections are considered: point to point, bus based, and networks-on-chip (NoCs). Most systems require communicating with other external elements. The requirements of such off-chip communication are dependent on many factors: speed, reliability, distance, environmental conditions, compatibility with networks, and so on. The chapter addresses the in-chip communications, covering point-to-point communications, bus-based connections, and NoCs. Since FPGAs integrate multiple computing resources, it is also necessary to establish some basics on how to efficiently implement communications between modules inside the chip. Low-Speed Interface communication schemes are intended for control purposes or for low- data-intensive applications, where only small amounts of data are exchanged. High-speed interfaces are packet-based synchronous communication interfaces with clock recovery at the receiver end since it is not possible to transmit the clock as an additional line.