ABSTRACT
This chapter discusses various concerns regarding the process, material, and device characteristics of the-state-of-the-art subnanometer high-k gate dielectrics. It highlights some potential options for future high-k processes. The scaling of gate dielectric physical thickness has been the major strategy for maintaining continuous downsizing and performance improvement of metal oxide semiconductor (MOS) devices for several decades. This scaling had once reached its technological limit at around 1 nm before the introduction of high-k gate dielectric materials. The chapter highlights various fundamental issues in the introduction of high-k materials, technological issues of thin film preparation, and electrical characteristics of advanced complementary metal–oxide–semiconductor (CMOS) devices based on state-of-the-art metal gate/high-k stacks. To further lower the equivalent oxide thickness (EOT) of gate dielectric films to around half nanometer, which is likely to be used in the technology node with the gate length of 6 nm, even higher-k-value materials and better interface layer control are indispensable.
