ABSTRACT
This chapter describes the simulation studies and developments of technology computer-aided design (TCAD)-based variability-aware design technology co-optimization (DTCO) methodology for the latest fin field-effect transistor (finFET) technology. More specifically, using the 14 nm silicon-on-insulator (SOI) finFET as a test vehicle, the authors show how different sources of variability influence the performance of finFETs and corresponding 6T- static random access memory (SRAM) cells. In order to highlight the features and importance of TCAD-based variability-aware DTCO process, the simulations of variability, statistical compact model extraction and generation, and stochastic circuit simulations and verifications have been included in the chapter. The chapter focuses on both groups: global variability and local variability. It examines in detail how different variability sources influence the device performance in 14 nm SOI finFETs and corresponding 6T-SRAM cells. The chapter demonstrates the TCAD-based variability-aware DTCO process, including simulations of variability, variability-aware compact model extraction and generation, and statistical circuit evaluations and verifications in 14 nm finFET technology.
