ABSTRACT
This chapter describes the delay metric outcomes based on the choice of the high-k spacer material and its length in FinFET logic circuit applications. Double/tri-gate FinFETs are recognized as one of the most promising successors of conventional bulk MOS devices in the sub-20 nm regime due to their excellent short-channel characteristics and reduced leakage currents. The two main inherent challenges associated with the FinFET are the higher magnitude of parasitic due to its three-dimensional (3D) architecture and the fin width quantization. To evaluate the FinFET logic circuit performance, mixed-mode circuit simulations of a FinFET inverter and the three-stage ring oscillator (RO3) circuits have been carried out. The p-type to n-type width ratio of a FinFET inverter is tuned to 2:1 to obtain symmetrical voltage transfer characteristics (VTC) and to maximize the noise margins. A sharp transition region improves the noise margins (NMH, NML) of an inverter; that in turn, enhances stability.
