ABSTRACT
This chapter investigates the proposed symmetric (SymD-k) and asymmetric dual-k (AsymD-k) architectures in the 6T-static random-access memories (SRAM) cell. It distinguishes the proposed SymD-k–based SRAM cell helps in improving the hold, read and write noise margins, read/write speed, and standby leakage power without affecting pull-up ratio (PR) and cell ratio (CR). The chapter presents the brief introduction of a basic SRAM architecture and bit cell, its read/write operations, and the performance evaluation metrics such as static noise margins (SNM), access time, and standby leakage power. It explores the proposed symmetric and asymmetric dual-k configurations, and their merits and demerits over the conventional and purely high-k architectures. The chapter also investigates the effect of supply voltage on dual-k–based SRAM cells. An SRAM cache consists of an array of bistable memory bit cells along with the address decoders, sense amplifiers, write drivers, and bit-line precharge circuits commonly known as the peripheral circuitry.
