ABSTRACT
To meet the requirements of next-generation information and communication technology (ICT) systems, the packaging technology has to evolve along with the silicon technology node scaling as predicted by Moore’s law. At the same time, design and development of packages have to meet the cost, performance, form factor, and reliability goals. In this chapter, we will examine the role of emerging 2.5-dimensional (2.5D) and 3-dimensional (3D) IC-packaging platforms for addressing the gap seen between the slowdown of Moore’s law scaling and the ever-increasing system integration requirements. System integration based on the 3D system-in-package (3D SiP) technology has been developed for integrating application-specific integrated circuits (ASICs) and memory devices. We will review the new elements introduced by 2.5D and 3D IC packaging and the potential risks to reliability of the final products. A detailed review on technology and component-level qualification will be presented. It will then be followed by two examples as case studies on board-level reliability validation.
