ABSTRACT
This chapter focuses on the development of a realistic process design kit (PDK) for academic use that overcomes these limitations. It describes the static random access memory design technology co-optimization (DTCO) and array development and performance in the ASAP7 predictive PDK. A key issue in the DTCO process is determining the worst-case spacing between any two metal structures with misalignment, so that the resulting process is reliable against Time-Dependent Dielectric Breakdown. Lithography plays a leading role in the scaling process, which is the industry’s primary growth driver, as it determines the extent to which feature geometries can be shrunk in successive technology nodes. Lithography is one of the most expensive and complex procedures in semiconductor manufacturing, with mask manufacturing being the most expensive processing steps within lithography. Patterning cliffs mark the pitch limits for a given lithography technique or Multiple Patterning approach.
