ABSTRACT
Voltage scalability is intimately tied with extendibility of nonvolatile memorie (NVM) device properties along with feature-size scalability. The feature size scalability in silicon based NVM technology thus far has been primarily horizontal. During the last decade, several investigators have proposed stack designs replacing oxide in SONOS layers with high K insulators for voltage scaling and enhancement of device characteristics. With the exception of, which created a novel charge trapping dielectric layer by plasma nitridation of oxide to contain 22" nitrogen to provide high density of deep traps, other proposals consisted of high K dielectric films to replace either charge blocking layer, or both tunnel layer and charge blocking oxide layer, or even all layers of SONOS including nitride trapping layer. In all cases, the EOT for stack was reduced to lower programming voltages. Eventually, all high K layers were used for charge-trapping (CT) device functions of tunneling, trapping, and charge blocking to reduce stacks EOT, thereby reducing programming voltage levels.
