ABSTRACT
Tunnel-based nonvolatile memories (NVMs) devices require injection of electrons and/or holes either from the silicon substrate or from the gate electrode. The normal mode NVM device stacks are designed to minimize gate charge injections during writing and erasing, while the reverse mode NVM device stacks are designed to minimize charge injections from the silicon substrate. This chapter examines the importance of high K dielectric and barrier engineering in the gate stack design in scaling Vpp. It aims to the conventional NVM device stack design employing conventional dielectric films described in. The chapter discusses primary considerations of stack designs of conventional FG-NAND flash devices and CT NROM random access NVMs. In the latter type of devices, Nanocrystal (NC) characteristics in terms of size, density, distribution, and work function influencing NVM properties have also been covered.
