ABSTRACT
Silicon based nonvolatile memories (NVMs) cells are variations of FET cells and have evolved and integrated along with the development of CMOS FET devices, circuits, and technology. Multifaceted progress was made in floating-gate cell types and density, array designs, multilevel store capability, and technology integration with existing CMOS technology making the FG-NVM the primary memory product for the NVM industry. Such progress was aided by the progress made in defect control and yield of the relatively thicker tunnel oxide process technology employed for the FG-NVM cells. Disturbs are related to stability of memory states of NVM cells due to operational stresses experienced by the cells when cells associated with the word lines and/or bit lines are read or written or erased. Disturb characteristics differ on cell design, operational conditions, and array architecture and should be evaluated, minimized, and contained within the margins of the memory states of the specific types of nonvolatile device types and arrays.
