ABSTRACT
Since 1965, integrated circuit (IC) complexity has doubled approximately every 18 months in accordance with Moore’s Law [7,30]. Modern ICs incorporate multiple cores and peripherals comprising billions of transistors (e.g., [28]). Three-dimensional (3D) integration has emerged as a promising technology for IC scaling. With 3D stacking, the length of global wires can be reduced by as much as 50%, wire-limited clock frequency can be increased by 3.9, and wire-limited area can be decreased by 84% [19]. Additionally, power can be reduced by 51% at the 45 nm technology node [3]. 3D-ICs are enabled by vertical front-to-back electrical connections within the die. The vertical interconnect is provided by through-silicon-vias (TSVs) in bulk processes [32] and by through-oxide-vias (TOVs) in silicon-on-insulator (SOI) processes [8]. In both bulk and SOI, a metal interconnect (plug) is fabricated through the die; in bulk processes, an insulator (the liner) is also fabricated to isolate the metal plug from the substrate.
This chapter addresses the analysis and mitigation of TSV-to-device coupling noise within 3D-ICs. Coupling arises due to a signal traveling through the TSV in close proximity to MOS devices (Figure 13.1). The signal propagates through the TSV liner and the substrate, changing the body voltage of nearby devices. While the shift in body voltage resulting from fast (5–50 ps) rise/fall TSV signal-times is small, coupling noise can impact circuit performance, especially for analog circuits requiring a high-degree of noise isolation. Accurate modeling and analysis of TSV-to-device noise is thus needed. Further, noise can be suppressed using noise-mitigation techniques. For 2D-ICs, several techniques, including split power planes, deep-n-well process, and guard ring structures, are employed for noise isolation. While some of these techniques can be utilized in 3D-ICs, high TSV densities and the associated area penalties call for innovative, less costly isolation methods. 3D-stacked dies with TSV interconnect. The Cu-TSV is surrounded by an SiO<sub>2</sub> liner. TSVto-device coupling occurs when a signal traveling through the TSV propagates through the liner and the Si substrate, changing the body voltage of neighboring devices. https://s3-euw1-ap-pe-df-pch-content-public-p.s3.eu-west-1.amazonaws.com/9781315214306/963a4f3b-ca0a-40a0-956b-53cf3973ad6f/content/fig13_1.tif"/>
This chapter begins by reviewing recent advances in modeling TSV-to-device coupling and providing TSV coupling analysis to MOSFET and FinFET devices. The chapter then describes noise-mitigation techniques appropriate for 3D-ICs. The chapter concludes with a summary and outlines some future challenges. The reviewed material appears in more depth in two theses [16,26] and in related publications [15,23,25].
