Hardware Description and Synthesis of DSP Systems

The design process for an application specific-architecture of a digital signal processing algorithm is shown in Fig. 27.1. This process consists of the following steps. Beginning with a known algorithm, such as a finite impulse response (FIR) filter, the design is mapped onto functional units. This process can be automated using high level synthesis tools [1]–[11]. Once the functional blocks and the connection topology have been identified, it is necessary to begin mapping the architecture onto a physical design. This process can be automated by using hardware description languages such as Verilog or VHDL to first describe the functional blocks. Finally the hardware description modules can be mapped to a particular physical implementation using logic synthesis. Figure 27.1 Design flow using hardware description. https://s3-euw1-ap-pe-df-pch-content-public-p.s3.eu-west-1.amazonaws.com/9781315214719/0fb871de-cdc7-4110-bdc0-1b5d88b350ec/content/fig27_1.tif"/>