ABSTRACT
Grace Zgheib, Hadi Parandeh-Afshar, David Novo and Paolo Ienne
EPFL, Lausanne, CH
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.2 And-Inverter Cone Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3 AIC Cluster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.4 AIC-Based FPGA Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.4.1 Pure AIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.4.2 Hybrid LUT/AIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5 Shadow AIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.6 CAD Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.6.1 Technology Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.6.1.1 Definitions and Problem Formulation . . . . . . . . 140 5.6.1.2 Generating All Cones . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.6.1.3 Forward Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.6.1.4 Backward Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.6.1.5 Area Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.6.2 Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Semiconductor manufacturing costs are increasing drastically as technology keeps on reducing transistor feature size. As a result, the volume required to achieve an economical advantage from the latest technology nodes-certainly the main driving force of CMOS scaling-is becoming unreachable for most IC designs. These designs are relegated to either stop benefiting from Moore’s Law and remain in an old technology node or access the latest technology node through reconfigurable hardware. Indeed, reconfigurable hardware such as Field-Programmable Gate Arrays (FPGAs) start to have a privileged access to the most advanced technology nodes due to their scaling-friendly regular
and
FIGURE 5.1: A 3-level And-Inverter Cone (3-AIC).
