ABSTRACT
The ΔΣ modulation has become an important technique not only in the area of data conversion but also in the area of clock and frequency generation these days. In wireless systems, frequency synthesizers based on the ΔΣ fractional-N phase-locked loop (PLL) greatly relax design requirements such as the in-band phase noise and the settling time [1-5]. Moreover, the ΔΣ fractional-N PLL enables direct digital frequency modulation for lowcost transmitter design [3,6-8], thus becoming a key building block in modern transceiver systems. Recent development of the digital-intensive PLL (DPLL) offers solid frequency generation over the gate leakage current and the loop parameter variation problems over process and temperature variations [9-11]. In the DPLL, the ΔΣ modulator is used to enhance the resolution of the digitally controlled oscillator (DCO) and to improve the performance
CONTENTS
10.1 Introduction ................................................................................................ 261 10.2 Overview of the ΔΣ Modulation Method ............................................... 262 10.3 Hybrid FIR Filtering Technique ...............................................................264 10.4 Clock and Frequency Generation with FIR-Embedded
ΔΣ Modulation ............................................................................................ 267 10.4.1 Digital Clock Generation with Wideband PLL.......................... 268 10.4.2 FIR-Embedded ΔΣ DLL with Fine Resolution ........................... 268 10.4.3 Fractional-N Frequency Synthesizer with Customized
Noise Shaping ................................................................................. 270 10.4.4 Finite-Modulo Fractional-N PLL with Reduced Spur .............. 270 10.4.5 FIR-Embedded DCO Modulation ................................................ 272 10.4.6 FIR-Embedded Two-Point Modulation for Transmitter ........... 272
10.5 Conclusion .................................................................................................. 276 References ............................................................................................................. 276
of the time-to-digital converter (TDC) with dithering. In wireline systems, the ASIC-based system-on-chip (SoC) design with standard CMOS technology enforces the use of the DPLL for robust clock generation and good technology scalability.
