ABSTRACT
Placement is an essential step in the physical design ow since it assigns exact locations for various circuit components within the chip’s core area. An inferior placement assignment will not only aect the chip’s performance but might also make it nonmanufacturable by producing excessive wirelength, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands. Typical placement objectives include total wirelength, timing, congestion, and power. In this chapter, we survey the main algorithmic methods used in stateof-the-art placers.
