ABSTRACT
Since their introduction in the early 1980s, Field-Programmable Gate Arrays (FPGAs) have evolved from implementing small glue-logic designs to implementing large complete systems. Programmable logic devices range from lower-capacity nonvolatile devices such as Altera MAX™, Xilinx CoolRunner™, and MicroSemi ProASIC™ to very-high-density static RAM (SRAM)-programmed devices with signicant components of hard logic (ASIC). e latter are commonly called FPGAs. Most of the interesting CAD problems apply to these larger devices, which are dominated by Xilinx (Virtex™, Kintex™, Artix™ families) and Altera (Stratix™, Arria™, Cyclone™ families) [1]. All of these are based on a tiled arrangement of lookup table (LUT) cells, embedded memory blocks, digital signal processing (DSP) blocks, and I/O tiles.
