ABSTRACT
This chapter discusses some fundamental concepts used in very large scale integrated (VLSI) architecture design. Then brief discussions are given to pipelining, retiming, parallel processing, and folding, which are techniques that can be used to manipulate circuits to tradeoff speed, silicon area, and power consumption. The minimum achievable latency of a sequential circuit is computed as the number of clock cycles between when the first output is generated and when the first input is available, multiplied by the minimum achievable clock period. For a circuit without any feedback loop, the critical path can be changed by adding registers to or deleting registers from the data paths using the pipelining technique. The minimum achievable clock period of an architecture consisting of feedback loops is limited by the iteration bound.
