ABSTRACT
This chapter introduces Low–density parity–check (LDPC) codes. The LDPC encoding can be done as a generator matrix multiplication. This encoder can be also implemented by shift–-register architectures. The chapter fcouses on LDPC decoders are much more complicated. Due to the high hardware efficiency and throughout–-area tradeoff, most of the LDPC decoders currently adopted in various systems are partial–-parallel designs for quasi–-cyclic codes. The chapter also focuses on the architectures of these decoders. Since the architectures for the one–-step majority–-logic decoding and bit–-flipping decoders are straightforward, and the Min–-sum algorithm is currently adopted in many LDPC decoders used in practical systems. These hardware units only account for a very small proportion of the overall LDPC decoder area.
