ABSTRACT
One of the foremost challenges of sustaining Moore’s law of doubling CMOS transistor density on an integrated circuit every 24 months is the rapid deterioration of short channel effects with decreasing channel length of the transistors. This has led to a rapid flurry of device research and technology development of fully depleted (FD) transistor architecture since the turn of the century, which are, in principle, more immune to short channel effects than their nondepleted counterparts. There are two classes of FD channel transistors: (a) single-gate planar silicon-on-insulator (SOI) transistors and (b) multigate Tri-gate or FinFET transistors on either bulk or SOI substrate. While each architecture has its pros and cons, recent trends suggest that Tri-gate transistors on bulk silicon substrate are increasingly becoming the leading transistor option for advanced logic manufacturers. This chapter reviews the essential physics of operation of Tri-gate transistors.
