ABSTRACT
In Chapter 6, a generic flowchart of the digital signal process (DSP) was introduced (see Figure 6.1). This diagram is now reintroduced here in which the clock/timing recovered signals feeding back into the sampling unit of the analog-to-digital convertor (ADC) so as to obtain the correct timing for sampling the incoming data sequence for processing in the DSP. Any errors made at this stage of the timing will result in high deviation of the bit error rate (BER) in the symbol decoder shown in Figure 13.1. It is also noted that the vertical polarized (V-pol) and horizontal polarized (H-pol) channels are detected, and their in-phase (I-) and quadrature (Q-) components are produced in the electrical domain with signal voltage conditioned for the conversion to digital domain by the ADC.
