ABSTRACT
As graphene field-effect transistor (GFET) fabrication technology advances, compact models are needed to perform circuit-level simulations, in order to progress from device technology to circuit development. This chapter derives a compact model for graphene device and explores for circuit simulation applications. It examines the behavior of fabricated with monolayer and few-layer graphene materials. The chapter shows that saturation characteristics are intrinsic to the GFET, due to the cubic dependence of the drain current on drain–source voltage or velocity saturation effects. It describes a model for GFET modeling, based on its physical and electronic structure and implemented in a compact, closed form in industry-standard simulator Agilent Advanced Design System. Scaling of the gate dielectric, by either decreasing the oxide thickness or increasing the dielectric constant of the material, can increase the oxide capacitance at the gate. This increase in oxide capacitance yields performance improvement, with the limiting case being referred to as the quantum capacitance limit.
