ABSTRACT
Verification activities include review, analysis, and test. This chapter uses “testbench” as a synonym for a test procedure used in simulation because in the world of HDL (in particular VHDL) they serve a similar purpose. “Test procedure” will be used in its literal sense that is when referring to procedures used for hardware test. An effective technique is to start with a plan to organize the verification strategy. Each hardware requirement should be assessed as to whether it is suitable for review, analysis, and/or test. The optimal method for verifying each requirement is then selected and documented. For PLD requirements, the functional simulation and post-layout timing model is best suited to the analysis environment. Timing analysis can be targeted to post-layout timing models in the simulation tool, using the static timing analysis report from the layout tool or a combination thereof. A functional failure path analysis is performed prior to the verification process.
