ABSTRACT
The increasing speed and complexity of today’s designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. The use of portable devices and popular demand on battery life has made power consumption even more important in modern complementary metal–oxide–semiconductor (CMOS) designs. To meet this challenge, various techniques extending from the circuit level to the architectural level have been proposed aimed at reducing the consumed energy. Some circuit-level mechanisms include adaptive substrate biasing, dynamic supply scaling, dynamic frequency scaling, and supply gating [1,2].
