ABSTRACT
In this context, and complementary to previous works based on accelerated tests, Just et al. (2013) proposed a new type of experiment, based on a long-term exposure of fully processed wafers (with functional chips) to natural radiation background, in order to experimentally quantify the impact of atmospheric neutrons on flash memory circuits. The key point of this approach is to use a high density of devices at wafer level instead of a collection of stand-alone packaged circuits; this is possible because floating-gate (FG) memories do not require any circuitry or power supply except during the writing and read operations. One can thus envisage exposing wafers to natural radiation and then periodically reading wafers on which a large number of memory arrays have been initially programmed and characterized. In the same study, Just et al. (2013) also developed a numerical simulation code capable of computing the SER of FG flash memories. Our simulation platform, named TIARA-G4 and described in (Autran et al. 2012a), has been adapted to flash memory architectures (TIARA-G4 NVM release for nonvolatile memories) by modifying the device/circuit 3D geometries and by implementing a model for charge loss from the FGs induced by ionizing particles (Autran et al. 2014). This chapter presents in detail the modeling and simulation approach as well as the code validation by comparison of numerical results with experimental data reported in Just et al. (2013).
