ABSTRACT
The microelectronics industry has experienced tremendous progress in the last 40 years, especially with regard to the evolution of the performance of the products (i.e., integrated circuits) and, at the same time, the drastic reduction of manufacturing costs by elementary integrated function. So far, this considerable growth of the semiconductor industry has been due to its technological capability to constantly miniaturize the elementary components of circuits, namely the metal-oxide-semiconductor field effect transistor (MOSFET), the basic building block of very-large-scale-integration (VLSI) integrated circuits. The continuous decrease of the silicon surface occupied by these elementary components has kept the speed of integration at the pace dictated by the famous Moore’s law, which states that the number of transistors per integrated circuit doubles every 18-24 months (Moore 1965). However, in recent decades conventional bulk MOSFET scaling has encountered serious physical and technological limitations, mainly related to gate-oxide (SiO2) leakage currents (Gusev et al. 2006; Taur et al. 1997), a large increase in parasitic short-channel effects, and dramatic mobility reduction (Fischetti and Laux 2001) due to highly doped silicon substrates necessarily used to reduce these short-channel effects. Technological solutions have been proposed in order to continue to use the bulk solution until the 32-38 nm nodes (ITRS 2013). Most of these solutions have introduced high-permittivity gate dielectric stacks (to reduce the gate leakage) (Houssa 2004), a midgap metal gate (to suppress the silicon-gate polydepletion-induced parasitic capacitances), and strained silicon channels (to increase carrier mobility) (Rim et al. 1998). However, in parallel to these efforts, alternative solutions to replace the conventional bulk MOSFET architecture have been proposed and studied in the recent literature. These options are numerous, and can be classified in general according to three main directions: (i) use of new materials in the continuity of the bulk solution, allowing MOSFET performance to be increased due to their dielectric properties (permittivity), electrostatic immunity (silicon-on-insulator materials), mechanical (strain), or transport (mobility) properties; (ii) a complete change of device architecture (e.g., multiple-gate devices, silicon-nanowire MOSFETs) allowing better electrostatic control, and, as a result, intrinsic channels with higher mobilities and currents; and (iii) exploitation of certain new physical phenomena that appear at the nanometer scale, such as quantum ballistic transport, substrate orientation, or modifications of the material band structure in devices/wires with nanometer dimensions (Haensch et al. 2006; Hiramoto et al. 2006).
