Low-Power Techniques for Network-on-Chip

This chapter addresses different low-power techniques that have been adopted in the network-on-Chip (NoC) paradigm. It discusses the different power components and also discusses the standard low-power methods for NoC routers and links, respectively. The principle of power gating is to selectively powering down certain blocks in the chips while keeping other blocks powered up. The chapter describes the different system-level power reduction techniques such as dynamic voltage scaling, dynamic frequency scaling, voltage–frequency island partitioning, and runtime power gating. High-to-low voltage level shifter design has essentially two inverters in series, so it introduces only a single buffer delay. Multivoltage designs present significant challenges in placement. The chapter presents an overview of the following methods: clock gating, gate-level power optimization, multi-V_DD, multi-V_T, and power gating. In fine-grain power gating, the switch is placed locally inside each standard cell. The principle of power gating is to selectively powering down certain blocks in the chips while keeping other blocks powered up.