ABSTRACT
This chapter looks into a few strategies to solve the application-specific networks-on-chip (ASNoC) synthesis problem. It addresses system-level floorplanning to minimize NoC power consumption subject to layout constraints. Challenges in application specific NoC design have been surveyed in S. Benini. The chapter focuses on custom topology and route generation and also focuses on a scheme to intelligently put routers in a given NoC floorplan to optimize communication cost and energy consumed. It also looks into the strategies that do not consider the floorplan of the NoC. A holistic approach for application-specific NoC synthesis has been presented in G. Leary and K. S. Chatha. The chapter looks into an integer linear programming formulation for the minimization of the communication power consumption of the NoC. This power is given by the sum of the power consumed by the routers and the physical links. The chapter discusses a mixed integer linear programming-based approach to solve the NoC-centric floorplanning problem.
