ABSTRACT

This chapter describes circuits which realize a compact physical implementation of the spike timing-dependent plasticity (STDP) learning mechanism with biologically realistic action potentials. A great deal of the resulting research has been centered on implementing STDP. The chapter outlines the potential applications for a hardware implementation of the STDP learning rule. It has been recognized for some time that when implemented as single layer perceptron networks, STDP learning rules enable the identification of recurring spike patterns. The chapter focuses on Neuron circuits comprising of ambipolar nanocrystalline-thin film transistors (TFTs) and Nanoparticle memory TFTs (NP-TFTs) are simulated using simulation program with integrated circuit emphasis. Single memristive devices are used for the synapses, and are driven by the NP-TFTs connected to the presynaptic neuron outputs. Memory characteristics of the NP-TFT are modeled by adjusting the actual gate voltage of the intrinsic ambipolar nano-crystalline silicon TFT using a dependent voltage source to account for charge trapped in the nanoparticles.