ABSTRACT
With the scaling of CMOS technology to the sub-90nm domain, yield and reliability of integrated circuits become increasing challenges to the designers as far as the design productivity and the design creativity gap is considered. This chapter presents an introductory overview of the various physical causes of process variations and reliability issues on nano-scale analog circuits. It makes the designers aware of the two most critical challenges of nano-scale analog circuit design. The fundamental difference between nanometer-scale circuits and those built in their predecessor technologies is that the nano-scale circuits are subject to a wide range of new effects that induce on-chip variations. The time independent variations of circuit performances are due to systematic and random variations of manufacturing process related parameters. The chapter attempts to make the designers aware of the two most critical challenges of nano-scale analog circuit design.
