ABSTRACT
As the conventional metal-oxide-semiconductor field-effect transistor (MOSFET) scaling reached its fundamental limits, several novel techniques have been investigated to extend the CMOS road map. One of these techniques is the introduction of strain in the silicon channel of a MOSFET to obtain higher mobility. Enhancement in mobility may also be obtained by choosing the substrate surface orientation. The major mobility enhancement technologies currently in use can be grouped in two main categories: substrate induced and process induced. Application of strain results in two effects: shift in the band energy and degeneracy splitting of electronic states. Electron mobility is increased by the degeneracy splitting of the conduction band minimum, so the speed of devices fabricated on strained Si is enhanced. One of the predecessors of process-induced strained Si to enhance MOSFET performance is the research that showed enhanced electron mobilities in n-type (100) Si/Si1-xGex multilayer heterostructures and hole mobilities in p-type (100) Si/i-Si1-xGex/Si double heterostructures in early 1980s [1].
