ABSTRACT
Dynamic random access memories (DRAM) is a volatile memory since information stored is destroyed once the power supply to it stops even for a short duration. One transistor cell became almost universal for fabricating DRAMs up to the highest density level. Though 4 Kbit DRAM cell would become industry standard in 1973, it was R. H. Dennard’s patent of 1968 which gave first memory cell using only one transistor. Noise minimization/elimination has always been a priority item in DRAMs. Feasibility of a Capacitor-Over-Bitline cell for 64 Mbit DRAM was verified by M. Sakao and others in 1990. Issues connected with the process technologies like isolation dimension scaling, memory cell transistor parasitics, reduction in cell capacitance, and non-reduction of bit line capacitance with scaling down have been identified. If problems are attended to satisfactorily, scaling-down effects on degrading DRAM cells such as increased parasitic resistance and node junction leakage, and variation of threshold voltage could be overcome.
