ABSTRACT
This chapter offers only a bird’s-eye view of some technological details of few developed transistors mainly used in dynamic random access memory (DRAM) circuits beyond the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET). Double gate MOSFET structure has widely been studied as it offers distinct advantages for scaling to very short gate lengths, though the complexity of the fabrication process was a major obstacle in adopting double gate complementary MOS (CMOS) architecture. The main attraction of FinFETs was their scalability and the process compatibility with the conventional planar MOSFETs in spite of the fact the FinFETs are basically Silicon-on-insulator MOSFETs. FinFETs are considered promising candidates for sub-50 nm range in CMOS scaling because of their small threshold swing and drain-induced barrier lowering and good short channel effect (SCE) immunity resulting from excellent gate controllability with thin Silicon substrate. FinFETs were considered excellent alternatives for nanoscale DRAM cell transistor because of several advantages including reduction in SCE.
