ABSTRACT
CMOS-based radio frequency (RF) and analog systems have made rapid inroads into the analog/wireless market. The digital-driven CMOS scaling into the sub-100 nm range has produced transistors with competitive RF performance characteristics. Silicon-on-insulator (SOI) technology has been widely adopted to help mitigate drain-induced barrier lowering, to suppress fringing fields and charge-sharing effects which have become dominant in short-channel CMOS technologies. SOI technology has been used in 65 and 45 nm CMOS technologies. CMOS device width is an important factor in deciding its performance and reliability. Narrow finger width devices are believed to be more prone to hot-carrier and total-dose radiation damage, as compared to larger finger width devices. Source/drain (S/D) metal contact spacing has been shown to have significant impact on device parasitics and thus RF performance in sub-100 nm CMOS technologies. Significant trade-offs exist between the performance and the reliability in short-channel length MOSFETs.
