ABSTRACT
In comparison with other analog-to-digital converters (ADC) and digital-to-analog converters (DAC), delta-sigma (Δ∑) data converters exhibit a reduced sensitivity to analog component matching. The performance of modulators with a multi-bit quantizer is affected by the nonlinearity of the internal DAC and the increasing loading of amplifiers. Δ∑ modulators can be exploited in the implementation of calibration stages required to improve the linearity of Nyquist converters. Built-in selftest is another application for analog signal synthesis where Δ∑ modulators are ideally suited. Δ∑ ADCs can be implemented using either continuous-time or discretetime filters. Δ∑ modulators are generally described by the order of the loop filter, the characteristic of which determines the shape of the noise spectrum. In general, the time-domain output waveform of Δ∑ modulators can be affected by idle tones or pattern noise, which appears as periodic impulses whose peak levels are much greater than their root-mean square values.
