ABSTRACT
As transistors are scaled down in the nanoscale regime, quantum effects are playing a crucial role on device performances and parameters. Moreover, scaling alone is not sufficient to achieve performance improvement, and new boosters and device concepts are needed. For instance, the trade-off between power and performance in electronics is one of the most limiting factors to push further technology scaling and development. With scaling, the reduction of supply voltage to keep power density under control [1-3], the rise of source and drain resistance due to film thickness reduction in order to keep good electrostatic control [3], and finally source-drain (SD) tunneling that degrades subthreshold slope and increases leakage of transistors below 10 nm [3-4], are major roadblocks that degrade on-and/or off-current,
6.1 Simulation Algorithm ................................................................................... 155 6.2 Gate Coupling Optimization in Nanoscale Nanowire MOSFETs:
Electrostatic Versus Quantum Confinement ................................................. 157 6.3 Physics of RT-FET ........................................................................................ 161
6.3.1 Influence of Barrier Width ................................................................ 165 6.4 Schottky Barrier RT-FET ............................................................................. 166 6.5 Conclusions ................................................................................................... 169 Acknowledgments .................................................................................................. 170 References .............................................................................................................. 170
and ION/IOFF ratios and therefore the power-delay trade-off of transistors. ION/IOFF ratios and slope characteristics of transistors depend on the gate-to-channel coupling and carrier statistics that dictate the way carriers are made available to drive a current when increasing VG. By reducing film thickness and increasing the number of gates, ultrathin film multigate silicon-on-insulator (SOI) architectures have better electrostatic control and can achieve near-ideal subthreshold slope and improved ION/IOFF ratio over more conventional bulk Si single-gate architectures. Assuming an ideal gate coupling, however, when varying the gate voltage, the current varies at a rate dictated by Fermi-Dirac statistics only. This is governed by the gate-controlled single-barrier paradigm on which present field-effect transistors (FETs) are based. In a standard transistor, there is only one barrier from channel-to-source and the density of state close to the top of the channel barrier is about constant with VG [5]. As a result, the current increase is exponential below threshold with an optimal minimal inverse subthreshold slope (SS) of kT/q log10, that is, about 60 mV/decade at T = 300 K. Above threshold, when the channel barrier passes below the source Fermi level, EFS, enabling the source highly occupied states to drive a significant current density, and thus good delay performance, the current increase is much slower and the inverse slope reaches much higher values.
