ABSTRACT
In accord with Moore’s law, the refinement of integrated circuit (IC) technology has been doubling the number of devices in a given chip area every 2 years. However, conventional device scaling is approaching its physical limits and physics-based constraints will force many changes in materials, processes, and device structures as the industry moves down to 32 nm and smaller designs. There are problems such as increasing capital investments (such as for better lithography tools), whereas technical problems such as increasing interconnect wire delays and gate leakage currents in the integrated circuits are becoming insurmountable barriers to sustaining past rates of performance growth.
