ABSTRACT
This chapter describes the test generation method used by timing-aware ATPG (TAA) for transition faults. To calculate the signal delays at each gate in a design accurately, timing-based simulation can be used to track the signal changes in time. A simplified method was proposed, and it represents each signal by two logic values and two time numbers: the earliest possible arrival time of the initial value and the latest possible stabilization time of the final value. This method is still not easy or efficient to integrate into the test generation for target faults due to unspecified values that exist during ATPG. For timing-aware test pattern generation, the transition arrival and fault effect propagation times are used to approximate the path delay through a fault site. After a test pattern/set of test patterns is generated, the traditional transition fault test generator simulates undetected faults to find the faults detected by chance and to drop them from the target fault list.
