ABSTRACT
The test method presented in this chapter reduces the risk of any false identification of good chips as faulty due to IR drop effects rather than small-delay defects. In addition, the method is timing aware and relatively fast for a large design. The chapter describes the physical synthesis of the case study design. Scan-based test insertion was performed with eight scan chains. During test mode, all the bidirectional pins are controlled in input mode to avoid any congestion problem. The delay scaling formulation provided in the chapter can be extended if the factors are different for each library cell. Although it increases the accuracy of the analysis, it also would significantly increase the computational complexity. To group the patterns with relatively close path delay distribution, the patterns were sorted in increasing order of pattern slack. The pattern slack is referred to as the least slack across all the endpoints in the respective pattern.
