ABSTRACT
The digital signal processing subsystems employed by complex radar systems (CRS) are used to solve various problems. One of the possible ways to increase the microprocessor subsystem performance and reliability during the digital signal processing in real time is to design and construct the multicomputer subsystems; these are used in CRSs to use effectively the digital signal processing algorithms. The chapter provides an opportunity to exploit the digital signal processing algorithms requiring larger memory size compared to a single-microprocessor subsystem, given the structural modifications of microprocessor subsystems with limited effective speed of operation and memory size. Microprocessors in the multicomputer subsystem may process the digital signal processing algorithms in off-line mode or while interacting with each other. The homogeneous multicomputer subsystem constructed based on these principles allows to realize any digital signal processing algorithms. Digital signal processing in CRSs is carried out in real time depending on the speed of incoming requests to realize the definite signal processing algorithms.
