Sequential Logic Design Using Verilog HDL

This chapter presents several examples of designing Moore and Mealy finite-state synchronous sequential machines by using Verilog hardware description language (HDL). The designs will utilize behavioral and structural modeling constructs and consist of sequence detectors and counters of various moduli. The chapter also presents a variety of asynchronous sequential machines that are designed using Verilog HDL. Verilog contains two structured procedure statements or behaviors: initial and always. Then, the chapter presents an important class of asynchronous sequential machines in which pulses trigger state changes. The set/reset (SR) latch and D flip-flop in a master-slave relationship is by far the most reliable method to implement pulse-mode asynchronous sequential machines. Another method to design pulse-mode machines is to use level-sensitive T flip-flops as storage elements that are designed with SR latches. The SR-T flip-flop possesses the combined operational characteristics of both the SR latch and the T flip-flop.