ABSTRACT
High-speed analog-to-digital converter (ADC) architectures have been developing for the past two decades to support the increasing requirements for data processing. High sampling rate converters are in great demand due to the advances in software-defined radio (SDR) architectures and the drive toward direct radiofrequency/intermediate frequency (RF/IF) sampling. Performance specifications for these communication systems dictate that ADC designs, in a low-cost process technology such as complementary metal oxide semiconductor (CMOS), must achieve high spurious-free dynamic range (SFDR) and low-power consumption. This chapter reviews the high-speed architectures and predicts their performance as the CMOS process technology scales down. It focuses on ADC architectures that can be beneficial in meeting the industry's application needs. The two well-known design approaches to ADC design are subsampling and oversampling architectures. The issue of ADC performance and power consumption in the nanotechnology era arises from the fact that integrating multiple communication system standards on a single chip would require many highly performing ADCs on the chip.
